December 3, 2021

5nm AMD Zen 4 Ryzen 6000 CPUs Coming in November 2022 [Rumor]

AMD might be launching its next-gen Ryzen household that includes the Zen 4 core structure and TSMC’s 5nm EUV course of node presently subsequent 12 months. This information was shared by @Greymon55 on Twitter and falls in keeping with what AMD has said previously. Together with the Ryzen 6000 processors, the chipmaker may also launch the 4th Gen Epyc Genoa and Bergamo server chips within the final quarter of 2022 and early 2023, respectively.

Each Genoa and Bergamo might be primarily based on TSMC’s N5 (5nm EUV) node. In response to AMD, Genoa will provide 2x the effectivity and 25% extra efficiency than the prevailing Epyc Milan chips. Along with a brand new socket (SP5), we’re DDR5 reminiscence help, PCIe Gen 5 plus CXL 1.1 integration as properly. Genoa will characteristic as many as 128 PCIe Gen 5 lanes in a 1S and 160 in a 2S configuration. The TDP will reportedly be elevated to 320W with a cTDP of as much as 400W.

Bergamo, then again, might be a devoted lineup for cloud suppliers. Though it’ll leverage the identical ISA (and socket) as Zen 4, the core complexes might be tweaked (most notably the cache) to pack sixteen cores in a single CCD (vs eight on Genoa). Bergamo will characteristic as much as 128 cores and is clearly a jab on the emergence of Arm-based designs within the cloud sector (akin to these from Amazon and Google).

Coming to the client-side, Ryzen 6000 ought to improve the core counts throughout the board. We should always see at the very least 18-20 cores on the Ryzen 9 SKUs, and 12 on the Ryzen 7. Ryzen 5 might or might not get bumped as much as 8. The cache and reminiscence subsystem of the Zen 4 household is as follows:

Now we have the L1 and L2 cache sizes which are available at 32KB and 1MB, respectively. As compared, Golden Cove has an L1D cache of 48KB and an L2 cache of 1.25MB. Zen 3 had the identical L1, however an L2 cache of 512KB, so we’re a 2x improve within the case of the latter. The L1 and L2 associativity are unchanged at 8-way set associative for each the L1 and L2 caches.

The L1I TLB has 64 4K pages, the L1D 72, and the L2 with 64 2M/4M. The L1I cache has 64 absolutely associative entries, the L1D 72, the L2 cache with 64, and the L3 with 72. The variety of entries for the L12 TLB is pegged at 512, 3072 for the L2D, and 512 for the L2I. Lastly, the associativity for the three is 4, 12, and a pair of, respectively. The L2D cache options 3072 entries with 12-way associativity.

The L3 cache is more likely to keep unchanged, though we would see 3D stacked V-cache along with the traditional L3 cluster. You possibly can learn extra about Intel’s Golden Cove and AMD’s Zen 3 core right here. The AM5 platform might be outfitted with DDR5 and PCIe Gen 5, and AM4 coolers might be suitable with the socket.

Additional studying:

AMD Zen 3D (V-Cache) CPUs to Launch in H1 2022, Zen 4 to Assist PCIe Gen 5, AM4 Coolers Appropriate w/ AM5

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