December 3, 2021

AMD Radeon RX 7900 XT/7800 XT to Characteristic 3D Stacked Infinity Cache [Rumor]


Based on the newest set of rumors from @Greymon55, AMD’s next-gen Radeon RX 7900 XT and 7800 XT is not going to solely function a chiplet design but in addition boast 3D stacked L3 cache. The upper-end Navi 31 and Navi 32 dies which is able to energy the following era of AMD’s high-performance gaming graphics playing cards are anticipated to function as much as 15,360 shaders. On the cache aspect, we’re taking a look at as much as 384-512MB of 3D stacked L3 “Infinity Cache”.

The Navi 31 (RX 7900 XT) flagship might be primarily based on an MCM (chiplet) design with a complete of over 15 thousand cores (15,360 to be precise). It ought to simply be 2.2-2.5x quicker than its predecessor, with the RX 7800 XT (Navi 33) beating the RX 6800 XT by 30-40%.

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AMD’s RDNA 3 graphics structure is predicted to get a significant overhaul on the front-end, with redesigned Work Group Processors instead of Compute Items, or Twin Compute Items. With RDNA 1 and a couple of, the WGPs had been the essential models for workload scheduling (from CUs on GCN/Vega), nevertheless it appears like that’s going to vary once more with Navi 3x. Twin Compute Items are being discarded in favor of wider Work Group Processors, packing as many as 256 stream processors throughout eight 32-wide SIMDs.

Every Graphics Die (GCD) options three Shader Engines that are made up of two Shader Arrays every. In flip, every Shader Array packs 5 WGPs containing eight SIMD models (vs 4 on RDNA 2). The 2 dies are linked by a bridge interconnect paired with 512MB of L3 “Infinity” Cache. Based on the supply, the GCDs might be fabbed on TSMC’s 5nm (N5) node whereas the MCD might be fabbed on the older 6nm (N6) node. Every die ought to include a 128-bit bus (divided into eight controllers), leading to an general bus width of 256-bit and the identical exterior bandwidth of 448GB/s because the RX 6800 XT/6900XT.

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